1. Technical Field
The present invention relates to an interfacing device for interfacing bit-parallel data buses of different bit width, a control unit of the interfacing device, and a logical cell for use in such a control unit.
2. Discussion of Related Art
Such an interfacing device is already known in the art, e.g. from the U.S. Pat. No. 4,309,754, entitled `Data interface mechanism for interfacing bit-parallel data buses of different bit width`.
Therein (cf. Col. 1, In. 39-45), an interface mechanism is described which includes register means, named a data register, and a selection means, called a selector circuitry and which interconnects a first data bus with a second data bus the first one being wider than the second one. In the direction from the wide to the narrow data bus, the selector circuitry is then used for connecting different portions of the data register to the narrower data bus, one at a time, in an appropriate sequence.
Such an interfacing device is useful in particular when several data handling units are connected to the ingoing side of the interfacing device, and different ones of these data handling units deliver only a portion of the data leaving simultaneously at the outgoing side of the device. This is for instance so when the outgoing sets of data bits are ATM (Asynchronous Transfer Mode) cell headers containing routing information only a portion of which is determined by for instance a RAM (random access memory).
The selector circuitry described in U.S. Pat. No. 4,309,754 is drawn in FIG. 1 of the aforementioned U.S. Patent and consists of a microprocessor, control program storage means, a direct memory access controller, an interrupt controller, a dual port storage memory means, and some other means. The selector circuitry hence is very complex in hardware.